1. Technical Field
The present disclosure relates to the field of video compression, particularly video compression using High Efficiency Video Coding (HEVC) that employ block processing.
2. Related Art
FIG. 1 depicts a content distribution system 100 comprising a coding system 110 and a decoding system 140 that can be used to transmit and receive HEVC data. In some embodiments, the coding system 110 can comprise an input interface 130, a controller 111, a counter 112, a frame memory 113, an encoding unit 114, a transmitter buffer 115 and an output interface 135. The decoding system 140 can comprise a receiver buffer 150, a decoding unit 151, a frame memory 152 and a controller 153. The coding system 110 and the decoding system 140 can be coupled with each other via a transmission path which can carry a compressed bitstream 105. The controller 111 of the coding system 110 can control the amount of data to be transmitted on the basis of the capacity of the receiver buffer 150 and can include other parameters such as the amount of data per a unit of time. The controller 111 can control the encoding unit 114 to prevent the occurrence of a failure of a received signal decoding operation of the decoding system 140. The controller 111 can be a processor or include, by way of a non-limiting example, a microcomputer having a processor, a random access memory and a read only memory.
Source pictures 120 supplied from, by way of a non-limiting example, a content provider can include a video sequence of frames including source pictures in a video sequence. The source pictures 120 can be uncompressed or compressed. If the source pictures 120 are uncompressed, the coding system 110 can have an encoding function. If the source pictures 120 are compressed, the coding system 110 can have a transcoding function. Coding units can be derived from the source pictures utilizing the controller 111. The frame memory 113 can have a first area that can be used for storing the incoming frames from the source pictures 120 and a second area that can be used for reading out the frames and outputting them to the encoding unit 114. The controller 111 can output an area switching control signal 123 to the frame memory 113. The area switching control signal 123 can indicate whether the first area or the second area is to be utilized.
The controller 111 can output an encoding control signal 124 to the encoding unit 114. The encoding control signal 124 can cause the encoding unit 114 to start an encoding operation, such as preparing the Coding Units based on a source picture. In response to the encoding control signal 124 from the controller 111, the encoding unit 114 can begin to read out the prepared Coding Units to a high-efficiency encoding process, such as a prediction coding process or a transform coding process which process the prepared Coding Units generating video compression data based on the source pictures associated with the Coding Units.
The encoding unit 114 can package the generated video compression data in a packetized elementary stream (PES) including video packets. The encoding unit 114 can map the video packets into an encoded video signal 122 using control information and a program time stamp (PTS) and the encoded video signal 122 can be transmitted to the transmitter buffer 115.
The encoded video signal 122, including the generated video compression data, can be stored in the transmitter buffer 115. The information amount counter 112 can be incremented to indicate the total amount of data in the transmitter buffer 115. As data is retrieved and removed from the buffer, the counter 112 can be decremented to reflect the amount of data in the transmitter buffer 115. The occupied area information signal 126 can be transmitted to the counter 112 to indicate whether data from the encoding unit 114 has been added or removed from the transmitter buffer 115 so the counter 112 can be incremented or decremented. The controller 111 can control the production of video packets produced by the encoding unit 114 on the basis of the occupied area information 126 which can be communicated in order to anticipate, avoid, prevent, and/or detect an overflow or underflow from taking place in the transmitter buffer 115.
The information amount counter 112 can be reset in response to a preset signal 128 generated and output by the controller 111. After the information counter 112 is reset, it can count data output by the encoding unit 114 and obtain the amount of video compression data and/or video packets which have been generated. The information amount counter 112 can supply the controller 111 with an information amount signal 129 representative of the obtained amount of information. The controller 111 can control the encoding unit 114 so that there is no overflow at the transmitter buffer 115.
In some embodiments, the decoding system 140 can comprise an input interface 170, a receiver buffer 150, a controller 153, a frame memory 152, a decoding unit 151 and an output interface 175. The receiver buffer 150 of the decoding system 140 can temporarily store the compressed bitstream 105, including the received video compression data and video packets based on the source pictures from the source pictures 120. The decoding system 140 can read the control information and presentation time stamp information associated with video packets in the received data and output a frame number signal 163 which can be applied to the controller 153. The controller 153 can supervise the counted number of frames at a predetermined interval. By way of a non-limiting example, the controller 153 can supervise the counted number of frames each time the decoding unit 151 completes a decoding operation.
In some embodiments, when the frame number signal 163 indicates the receiver buffer 150 is at a predetermined capacity, the controller 153 can output a decoding start signal 164 to the decoding unit 151. When the frame number signal 163 indicates the receiver buffer 150 is at less than a predetermined capacity, the controller 153 can wait for the occurrence of a situation in which the counted number of frames becomes equal to the predetermined amount. The controller 153 can output the decoding start signal 164 when the situation occurs. By way of a non-limiting example, the controller 153 can output the decoding start signal 164 when the frame number signal 163 indicates the receiver buffer 150 is at the predetermined capacity. The encoded video packets and video compression data can be decoded in a monotonic order (i.e., increasing or decreasing) based on presentation time stamps associated with the encoded video packets.
In response to the decoding start signal 164, the decoding unit 151 can decode data amounting to one picture associated with a frame and compressed video data associated with the picture associated with video packets from the receiver buffer 150. The decoding unit 151 can write a decoded video signal 162 into the frame memory 152. The frame memory 152 can have a first area into which the decoded video signal is written, and a second area used for reading out decoded pictures 160 to the output interface 175.
In various embodiments, the coding system 110 can be incorporated or otherwise associated with a transcoder or an encoding apparatus at a headend and the decoding system 140 can be incorporated or otherwise associated with a downstream device, such as a mobile device, a set top box or a transcoder.
The coding system 110 and decoding system 140 can be utilized separately or together to encode and decode video data according to various coding formats, including High Efficiency Video Coding (HEVC). HEVC is a block based hybrid spatial and temporal predictive coding scheme. In HEVC, input images, such as video frames, can be divided into square blocks called Coding Tree Units (CTUs) 200, as shown in FIG. 2. CTUs 200 can each be as large as 128×128 pixels, unlike other coding schemes that break input images into macroblocks of 16×16 pixels. As shown in FIG. 3, each CTU 200 can be partitioned by splitting the CTU 200 into four Coding Units (CUs) 202. CUs 202 can be square blocks each a quarter size of the CTU 200. Each CU 202 can be further split into four smaller CUs 202 each a quarter size of the larger CU 202. By way of a non-limiting example, the CU 202 in the upper right corner of the CTU 200 depicted in FIG. 3 can be divided into four smaller CUs 202. In some embodiments, these smaller CUs 202 can be further split into even smaller sized quarters, and this process of splitting CUs 202 into smaller CUs 202 can be completed multiple times.
With higher and higher video data density, what is needed are ways to more efficiently, rapidly and accurately encode and decode individual pictures in a group of pictures for HEVC.